View STM32F030X8_9086655.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. january 2019 ds9773 rev 4 1/93 stm32f030x4 stm32f030x6 STM32F030X8 stm32f030xc value-line arm ? -based 32-bit mcu with up to 256 kb flash, timers, adc, communication interfaces, 2.4-3.6 v operation datasheet - production data features ? core: arm ? 32-bit cortex ? -m0 cpu, frequency up to 48 mhz ? memories ? 16 to 256 kbytes of flash memory ? 4 to 32 kbytes of sram with hw parity ? crc calculation unit ? reset and power management ? digital & i/os supply: v dd = 2.4 v to 3.6 v ? analog supply: v dda = v dd to 3.6 v ? power-on/power down reset (por/pdr) ? low power modes: sleep, stop, standby ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x6 pll option ? internal 40 khz rc oscillator ? up to 55 fast i/os ? all mappable on external interrupt vectors ? up to 55 i/os with 5v tolerant capability ? 5-channel dma controller ? one 12-bit, 1.0 s adc (up to 16 channels) ? conversion range: 0 to 3.6 v ? separate analog supply: 2.4 v to 3.6 v ? calendar rtc with alarm and periodic wakeup from stop/standby ? 11 timers ? one 16-bit advanced-control timer for six-channel pwm output ? up to seven 16-bit timers, with up to four ic/oc, ocn, usable for ir control decoding ? independent and system watchdog timers ? systick timer ? communication interfaces ? up to two i 2 c interfaces ? fast mode plus (1 mbit/s) support on one or two i/fs, with 20 ma current sink ? smbus/pmbus support (on single i/f) ? up to six usarts supporting master synchronous spi and modem control; one with auto baud rate detection ? up to two spis (18 mbit/s) with 4 to 16 programmable bit frames ? serial wire debug (swd) ? all packages ecopack ? 2 table 1. device summary reference part number stm32f030x4 stm32f030f4 stm32f030x6 stm32f030c6, stm32f030k6 STM32F030X8 stm32f030c8, stm32f030r8 stm32f030xc stm32f030cc, stm32f030rc lqfp64 10 10 mm lqfp48 7 7 mm lqfp32 7 7 mm tssop20 6.4 4.4 mm www.st.com
contents stm32f030x4/x6/x8/xc 2/93 ds9773 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 arm ? cortex ? -m0 core with embedded flash and sram . . . . . . . . . . . . 12 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 13 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 17 3.9.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 17 3.10 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10.2 internal volt age reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.2 general-purpose timers (tim3, tim14..17) . . . . . . . . . . . . . . . . . . . . . . 20 3.11.3 basic timers tim6 and tim7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.5 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 inter-integrated circuit interfaces (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14 universal synchronous/asynchronous receiver/transmitter (usart) . . . 22
ds9773 rev 4 3/93 stm32f030x4/x6/x8/xc contents 4 3.15 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 45 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 45 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.17 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.18 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.19 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
contents stm32f030x4/x6/x8/xc 4/93 ds9773 rev 4 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.1 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.2 lqfp48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.3 lqfp32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4 tssop20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.5.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
ds9773 rev 4 5/93 stm32f030x4/x6/x8/xc list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f030x4/x6/x8/xc family device features an d peripheral counts . . . . . . . . . . . . . . . 10 table 3. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. internal voltage reference calibrati on values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. stm32f030x4/x6/x8/xc i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. stm32f0x0 usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. stm32f030x4/x6/x8/xc spi implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. stm32f030x4/6/8/c pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. alternate functions selected through gpioa_af r registers for port a . . . . . . . . . . . . . . . 34 table 13. alternate functions selected through gpiob_af r registers for port b . . . . . . . . . . . . . . . 35 table 14. alternate functions selected through gpioc_af r registers for port c . . . . . . . . . . . . . . . 37 table 15. alternate functions selected through gpiod_af r registers for port d . . . . . . . . . . . . . . . 37 table 16. alternate functions selected through gpiof_afr registers for port f. . . . . . . . . . . . . . . . 37 table 17. stm32f030x4/x6/x8/xc peripheral register bounda ry addresses . . . . . . . . . . . . . . . . . . . 39 table 18. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 21. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 22. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 23. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 table 25. typical and maximum current consumption from v dd supply at v dd = 3.6 v . . . . . . . . . . 47 table 26. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 48 table 27. typical and maximum consumption in stop and standby modes . . . . . . . . . . . . . . . . . . . 49 table 28. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 30. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 31. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 32. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 33. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 34. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 35. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 36. hsi14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 37. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 38. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 39. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 40. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 41. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 42. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 43. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 44. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 45. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 46. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 47. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
list of tables stm32f030x4/x6/x8/xc 6/93 ds9773 rev 4 table 48. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 49. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 50. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 51. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 52. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 53. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 54. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 55. iwdg min/max timeout period at 40 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 56. wwdg min/max timeout value at 48 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 57. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 58. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 59. lqfp64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 60. lqfp48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 61. lqfp32 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 62. tssop20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 63. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 64. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
ds9773 rev 4 7/93 stm32f030x4/x6/x8/xc list of figures 7 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. clock tree of stm32f030x4/x6/x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 3. clock tree of stm32f030xc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. lqfp64 64-pin package pinout (top view), for stm32f030x4/6/8 devices . . . . . . . . . . . . 25 figure 5. lqfp64 64-pin package pinout (top view), for stm32f030rc devices . . . . . . . . . . . . . . 25 figure 6. lqfp48 48-pin package pinout (top view), for stm32f030x4/6/8 devices . . . . . . . . . . . . 26 figure 7. lqfp48 48-pin package pinout (top view), for stm32f030cc devices . . . . . . . . . . . . . . 26 figure 8. lqfp32 32-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. tssop20 20-pin package pinout (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. stm32f030x4/x6/x8/xc memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 13. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 14. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 15. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 16. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 17. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 18. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 19. tc and tta i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 20. five volt tolerant (ft and ftf) i/o input characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 21. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 22. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 23. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 24. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 25. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 26. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 27. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 28. lqfp64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 29. lqfp64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 30. lqfp64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 31. lqfp48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 32. lqfp48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 33. lqfp48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 34. lqfp32 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 35. lqfp32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 36. lqfp32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 37. tssop20 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 38. tssop20 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 39. tssop20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
introduction stm32f030x4/x6/x8/xc 8/93 ds9773 rev 4 1 introduction this datasheet provides the ordering informat ion and mechanical device characteristics of the stm32f030x4/x6/x8/xc microcontrollers. this document should be read in conjun ction with the stm32f0x0xx reference manual (rm0360). the reference manual is available from the stmicroelectronics website www.st.com . for information on the arm ? (a) cortex ? -m0 core, please refer to the cortex ? -m0 technical reference manual, available from the www.arm.com website. a. arm is a registered trademark of arm limited (o r its subsidiaries) in the us and/or elsewhere.
ds9773 rev 4 9/93 stm32f030x4/x6/x8/xc description 24 2 description the stm32f030x4/x6/x8/xc microcontrolle rs incorporate the high-performance arm ? cortex ? -m0 32-bit risc core operating at a 48 mhz frequency, high-speed embedded memories (up to 256 kbytes of flash memory and up to 32 kbytes of sram), and an extensive range of enhanced peripherals and i/os. all devices offer standard communication interfaces (up to two i 2 cs, up to two spis and up to six usarts), one 12-bit adc, seven general-purpose 16-bit time rs and an advanced-control pwm timer. the stm32f030x4/x6/x8/xc microcontrollers operate in the -40 to +85 c temperature range from a 2.4 to 3.6v power supply. a comprehensive set of power-saving modes allows the design of low-power applications. the stm32f030x4/x6/x8/xc microcontrollers include devices in four different packages ranging from 20 pins to 64 pins. depending on the device chosen, different sets of peripherals are included. the description below provides an overview of the complete range of stm32f030x4/x6/x8/xc peripherals proposed. these features make the stm3 2f030x4/x6/x8/xc microcontrollers suitable for a wide range of applications such as application control and user interfaces, handheld equipment, a/v receivers and digital tv, pc peripherals, gaming and gps platforms, industrial applications, plcs, inverters, printers, scanners, alar m systems, video intercoms, and hvacs.
description stm32f030x4/x6/x8/xc 10/93 ds9773 rev 4 table 2. stm32f030x4/x6/x8/xc family de vice features and peripheral counts peripheral stm32 f030f4 stm32 f030k6 stm32 f030c6 stm32 f030c8 stm32 f030cc stm32 f030r8 stm32 f030rc flash (kbytes) 16 32 32 64 256 64 256 sram (kbytes) 4 8 32 8 32 timers advanced control 1 (16-bit) general purpose 4 (16-bit) (1) 5 (16-bit) basic - 1 (16-bit) (2) 2 (16-bit) 1 (16-bit) (2) 2 (16-bit) comm. interfaces spi 1 (3) 2 i 2 c1 (4) 2 usart 1 (5) 2 (6) 62 (6) 6 12-bit adc (number of channels) 1 (9 ext. +2 int.) 1 (10 ext. +2 int.) 1 (10 ext. +2 int.) 1 (10 ext. +2 int.) 1 (10 ext. +2 int.) 1 (16 ext. +2 int.) 1 (16 ext. +2 int.) gpios 15263939375551 max. cpu frequency 48 mhz operating voltage 2.4 to 3.6 v operating temperature ambient operating temperat ure: -40c to 85c junction temperature: -40c to 105c packages tssop20 lqfp32 lqfp48 lqfp64 1. tim15 is not present. 2. tim7 is not present. 3. spi2 is not present. 4. i2c2 is not present. 5. usart2 to usart6 are not present. 6. usart3 to usart6 are not present
ds9773 rev 4 11/93 stm32f030x4/x6/x8/xc description 24 figure 1. block diagram 1. timer6, timer15, spi, usart2 and i2c2 are available on stm 32f030x8/c devices only. 2. usart3, usart4, usart5, usart6 and time r7 are available on st m32f030xc devices only. msv32137v3 4 channels 3 compl. channels brk, etr input as af @ v dd @ v dda system and peripheral clocks pa[15:0] pb[15:0] pc[15:0] 55 af @ v dda v dda v ssa swclk swdio as af 16x ad input osc_in osc_out osc32_in osc32_out tamper-rtc (alarm out) hsi14 hsi lsi pllclk ir_out as af 1 channel 1 compl, brk as af 1 channel 1 compl, brk as af 1 channel as af 4 ch., etr as af gp dma 5 channels cortex-m0 cpu f max = 48 mhz serial wire debug nvic ext. it wkup spi1 spi2 syscfg if dbgmcu window wdg apb ahb crc reset & clock control power controller xtal osc 4-32 mhz ind. window wdg sram 4/8/32 kb temp. sensor if 12-bit adc rtc rtc interface rc 14 mhz rc 8 mhz rc 40 khz pll ahb decoder xtal32 khz sram controller bus matrix flash memory interface flash gpl 16/32/64/256 kb 32-bit obl 2 channels 1 compl, brk as af rx, tx,cts, rts, ck, as af rx, tx,cts, rts, ck, as af rx, tx,cts, rts, ck, as af rx, tx,cts, rts, ck, as af scl, sda, as af scl, sda, smba (20 ma fm+), as af i2c1 i2c2 gpio port f gpio port d gpio port c gpio port b gpio port a pd2 pf[1:0] pf[7:4] supply supervision power @ v dda @ v dd v dd18 por reset int v dd = 2.4 to 3.6 v v ss nrst v dda v ssa v dd por/pdr volt.reg 3.3 v to 1.8 v usart4 usart3 usart2 usart1 timer 17 timer 16 timer 15 timer 14 timer 3 pwm timer 1 power domain of analog blocks : v dd v dda rx, tx,cts, rts, ck, as af rx, tx,cts, rts, ck, as af usart6 usart5 timer 7 timer 6 mosi, miso, sck, nss, as af mosi, miso, sck, nss, as af
functional overview stm32f030x4/x6/x8/xc 12/93 ds9773 rev 4 3 functional overview 3.1 arm ? cortex ? -m0 core with embedded flash and sram the arm ? cortex ? -m0 processor is the latest generat ion of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count a nd low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm ? cortex ? -m0 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f0xx family has an embedded arm core and is therefore compatible with all arm tools and software. figure 3 shows the general block diagram of the device family. 3.2 memories the device has the following features: ? 4 to 32 kbytes of embedded sram access ed (read/write) at cpu clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail- critical applications. ? the non-volatile memory is divided into two arrays: ? 16 to 256 kbytes of embedded flash memory for programs and data ? option bytes the option bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, th e flash memory cannot be read from or written to if either debug features ar e connected or boot in ram is selected ? level 2: chip readout protection, debug features (cortex ? -m0 serial wire) and boot in ram selection disabled 3.3 boot modes at startup, the boot pin and boo t selector option bit are used to select one of the three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart on pins pa14/pa15 or pa9/pa10.
ds9773 rev 4 13/93 stm32f030x4/x6/x8/xc functional overview 24 3.4 cyclic redundancy che ck calculation unit (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/i ec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes ? v dd = 2.4 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through vdd pins. ? v dda = from v dd to 3.6 v: external analog power supply for adc, reset blocks, rcs and pll. the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. for more details on how to c onnect power pins, refer to figure 13: power supply scheme . 3.5.2 power supply supervisors the device has integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the app lication design ensures that v dda is higher than or equal to v dd . 3.5.3 voltage regulator the regulator has two operating modes and it is always enabled after reset. ? main (mr) is used in normal operating mode (run). ? low power (lpr) can be used in stop mode where the power demand is reduced. in standby mode, it is put in power down mode. in this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and sram are lost).
functional overview stm32f030x4/x6/x8/xc 14/93 ds9773 rev 4 3.5.4 low-power modes the stm32f030x4/x6/x8/xc microcontrollers support three low-power modes to achieve the best compromise between low power cons umption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves very low power consum ption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the volt age regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti lines. the exti line source can be one of the 16 external lines and rtc. ? standby mode the standby mode is used to achieve the lo west power consumpt ion. the internal voltage regulator is s witched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the rtc domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pins, or an rtc event occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 3.6 clocks and startup system clock selection is perf ormed on startup, however the in ternal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resona tor or oscillator). several prescalers allow the a pplication to config ure the frequen cy of the ahb and the apb domains. the maximum freq uency of the ahb and t he apb domains is 48 mhz.
ds9773 rev 4 15/93 stm32f030x4/x6/x8/xc functional overview 24 figure 2. clock tree of stm32f030x4/x6/x8 1. applies to stm32f030x4/x6 devices. 2. applies to STM32F030X8 devices. msv32138v3 osc_in osc_out osc32_in osc32_out iwdg pllmul mco main clock output pllclk hsi hse hclk pllclk ahb, core, memory, dma, cortex fclk free-run clock lse lsi hsi hse rtc pllsrc sw mco rtcclk rtcsel sysclk tim1,3,6 (2) 14,15 (2) ,16,17 flitfclk flash memory programming interface hsi14 i2c1 usart1 lse hsi sysclk pclk sysclk hsi pclk cortex system timer apb peripherals lsi (1) lse (1) pllnodiv mcopre lse hse css legend white clock tree control element clock line control line black clock tree element /32 4-32 mhz hse osc /1,/2,/4, /8,/16 /1 (1) ,/2 14 mhz hsi14 rc /1,/2, /512 32.768 khz lse osc 40 khz lsi rc pll x2,x3,.. ...x16 x1, x2 /8 /1,/2,/4,.. ../128 usart1sw ppre ppre hpre i2c1sw sysclk hsi hsi 8 mhz hsi rc /2, /4 adc (14 mhz max) prediv /1,/2,.. ../16 /2 ckmode (1)
functional overview stm32f030x4/x6/x8/xc 16/93 ds9773 rev 4 figure 3. clock tree of stm32f030xc 3.7 general-purpose in puts/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. the i/o configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. msv47988v1 osc_in osc_out osc32_in osc32_out iwdg mco main clock output pllclk hsi hse hclk pllclk ahb, core, memory, dma, cortex fclk free-run clock lse lsi hsi hse rtc sw mco rtcclk rtcsel sysclk tim1,3,6,7 14,15,16,17 flitfclk flash memory programming interface hsi14 i2c1 usart1 lse hsi sysclk pclk sysclk hsi pclk cortex system timer apb peripherals lsi lse pllnodiv mcopre lse hse css legend white clock tree control element clock line control line black clock tree element /32 4-32 mhz hse osc /1,/2,/4, /8,/16 /1,/2 14 mhz hsi14 rc /1,/2, /512 32.768 khz lse osc 40 khz lsi rc x1, x2 /8 /1,/2,/4,.. ../128 usart1sw ppre ppre hpre i2c1sw sysclk hsi hsi 8 mhz hsi rc /2, /4 adc (14 mhz max) ckmode pllmul pllsrc prediv /1,/2,.. ../16 pll x2,x3,.. ...x16
ds9773 rev 4 17/93 stm32f030x4/x6/x8/xc functional overview 24 3.8 direct memory a ccess controller (dma) the 5-channel general-purpose dma manages memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hard ware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripheral s: spi, i2c, usart, all timx timers (except tim14) and adc. 3.9 interrupts and events 3.9.1 nested vectored interrupt controller (nvic) the stm32f0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of cortex ? -m0) and 4 priority levels. ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 extended interrupt/event controller (exti) the extended interrupt/event cont roller consists of 32 edge de tector lines used to generate interrupt/event requests and wake-up the system. each line can be independently configured to select the trig ger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains t he status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 55 gpios can be connected to the 16 external interrupt lines.
functional overview stm32f030x4/x6/x8/xc 18/93 ds9773 rev 4 3.10 analog to digital converter (adc) the 12-bit analog to digital converter has up to 16 external and two internal (temperature sensor, voltage reference measurement) channels and performs conversions in single-shot or scan modes. in scan mode, automatic conv ersion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrup t is generated when the converted voltage is outside the programmed thresholds. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as th e offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.10.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc. v refint is internally connected to the adc_in 17 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. table 3. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at a temperature of 30 c ( 5 c), v dda = 3.3 v ( 10 mv) 0x1fff f7b8 - 0x1fff f7b9 table 4. internal voltage reference calibration values calibration value name description memory address vrefint_cal raw data acquired at a temperature of 30 c ( 5 c), v dda = 3.3 v ( 10 mv) 0x1fff f7ba - 0x1fff f7bb
ds9773 rev 4 19/93 stm32f030x4/x6/x8/xc functional overview 24 3.11 timers and watchdogs the stm32f030x4/x6/x8/xc devices include up to five general-purpose timers, two basic timers and one advanced control timer. table 5 compares the features of the different timers. 3.11.1 advanced-c ontrol timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on six channels. it has complementary pwm output s with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the four independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or center-aligned modes) ? one-pulse mode output if configured as a standard 16-bit timer, it ha s the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard timers which have the same architecture. the advanced control timer can t herefore work together with the other timers via the timer link feature for sy nchronization or event chaining. table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs advanced control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 3 general purpose tim3 16-bit up, down, up/down any integer between 1 and 65536 yes 4 - tim14 16-bit up any integer between 1 and 65536 no 1 - tim15 (1) 16-bit up any integer between 1 and 65536 yes 2 1 tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6, (1) tim7 (2) 16-bit up any integer between 1 and 65536 yes 0 - 1. available on STM32F030X8 and stm32f030xc devices only. 2. available on stm32f030xc devices only
functional overview stm32f030x4/x6/x8/xc 20/93 ds9773 rev 4 3.11.2 general-purpose ti mers (tim3, tim14..17) there are four or five synchronizable general-purpose timers embedded in the stm32f030x4/x6/x8/xc devices (see table 5 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. tim3 stm32f030x4/x6/x8/xc devices feature one synchronizable 4-channel general-purpose timer. tim3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. it features four independent channels each fo r input capture/output compare, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim3 general-purpose timer can work wi th the tim1 advanced-control timer via the timer link feature for synchronization or event chaining. tim3 has an independent dma request generation. this timer is capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. the counter can be frozen in debug mode. tim14 this timer is based on a 16-bit auto-re load upcounter and a 16-bit prescaler. tim14 features one single channel for input capture/output compare, pwm or one-pulse mode output. its counter can be frozen in debug mode. tim15, tim16 and tim17 these timers are based on a 16-bit auto -reload upcounter and a 16-bit prescaler. tim15 has two independent channels, wher eas tim16 and tim17 feature one single channel for input capture/output compare, pwm or one-pulse mode output. the tim15, tim16 and tim17 timers can wo rk together, and tim15 can also operate withtim1 via the timer link feature for synchronization or event chaining. tim15 can be synchronized with tim16 and tim17. tim15, tim16 and tim17 have a complement ary output with dead-time generation and independent dma request generation. their counters can be frozen in debug mode. 3.11.3 basic time rs tim6 and tim7 these timers can be used as a generic 16-bit time base. 3.11.4 independent watchdog (iwdg) the independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it
ds9773 rev 4 21/93 stm32f030x4/x6/x8/xc functional overview 24 can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.11.5 system win dow watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb clock (pcl k). it has an early warnin g interrupt capability and the counter can be frozen in debug mode. 3.11.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source (hclk or hclk/8) 3.12 real-time clock (rtc) the rtc is an independent bcd timer/counter . its main features are the following: ? calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap year), 30, and 31 day of the month. ? programmable alarm with wake up from stop and standb y mode capability. ? periodic wakeup unit with programmable resolution and period (on stm32f030xc only). ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize the rtc with a master clock. ? digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. ? tow anti-tamper detection pins with prog rammable filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pi n, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32
functional overview stm32f030x4/x6/x8/xc 22/93 ds9773 rev 4 3.13 inter-integrated circuit interfaces (i 2 c) up to two i2c interfaces (i2c1 and i2c2) can operate in multimaster or slave modes. both can support standard mode (up to 100 kbit/s) or fast mode (up to 400 kbit/s). i2c1 also supports fast mode plus (up to 1 mbit/s), with 20 ma output drive. both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two addresses, one with configurable mask). they also include programmable analog and digital noise filters. in addition, i2c1 provides hardware su pport for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) generation/verification, timeouts verifications and alert protocol management the i2c interfaces can be served by the dma controller. refer to table 7 for the differences be tween i2c1 and i2c2. 3.14 universal synchronous/asyn chronous receiver/transmitter (usart) the device embeds up to six universal sync hronous/asynchronous receivers/transmitters that communicate at speeds of up to 6 mbit/s. table 6. comparison of i2c analog and digital filters - analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process - table 7. stm32f030x4/x6/x8/xc i 2 c implementation (1) 1. x = supported. i2c features i2c1 i2c2 (2) 2. only available on STM32F030X8/c devices. 7-bit addressing mode x x 10-bit addressing mode x x standard mode (up to 100 kbit/s) x x fast mode (up to 400 kbit/s) x x fast mode plus (up to 1 mbit/s), with 20ma output drive i/os x - independent clock x - smbus x - wakeup from stop - -
ds9773 rev 4 23/93 stm32f030x4/x6/x8/xc functional overview 24 table 8 gives an overview of features as implem ented on the available usart interfaces. all usart interfaces can be served by the dma controller. 3.15 serial peripheral interface (spi) up to two spis are able to commu nicate up to 18 mbit/s in slave and master modes in full- duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. spi1 and spi2 are identical and implement the set of features shown in the following table. table 8. stm32f0x0 usart implementation (1) usart modes/ features stm32f030x4 stm32f030x6 STM32F030X8 stm32f030xc usart1 usart1 usart2 usart1 usart2 usart3 usart4 usart5 usart6 hardware flow control for modem x xxxx - - continuous communication using dma x xxxxxx multiprocessor communication x xxxxxx synchronous mode x xxxxx - smartcard mode - ------ single-wire half-duplex communication x xxxxxx irda sir endec block- ------ lin mode - ------ dual clock domain and wakeup from stop mode - ------ receiver timeout interrupt x x-x--- modbus communication - ------ auto baud rate detection (supported modes) 2 2-2--- driver enable x xxxxx - usart data length 8 and 9 bits 7, 8 and 9 bits 1. x = supported.
functional overview stm32f030x4/x6/x8/xc 24/93 ds9773 rev 4 3.16 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. table 9. stm32f030x4/x6/ x8/xc spi implementation (1) 1. x = supported. spi features spi1 spi2 (2) 2. not available on stm32f030x4/6. hardware crc calculation x x rx/tx fifo x x nss pulse mode x x ti mode x x
ds9773 rev 4 25/93 stm32f030x4/x6/x8/xc pinouts and pin descriptions 33 4 pinouts and pin descriptions figure 4. lqfp64 64-pin package pinout (top view), for stm32f030x4/6/8 devices figure 5. lqfp64 64-pin package pi nout (top view), for stm32f030rc devices msv36496v2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vdd pc14-osc32_in pf0-osc_in nrst pc0 pc1 pc2 pc3 vssa vdda pa0 pa1 pa2 vdd pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa15 pa14 pf7 pf6 pa13 pa12 pa11 pa10 pa9 pa8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa3 pf4 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 lqfp64 pc13 pf5 vss vdd vss pf1-osc_out pc15-osc32_out io pins replaced by supply pairs for stm32f030rc devices. msv36483v2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vdd pc14-osc32_in pf0-osc_in nrst pc0 pc1 pc2 pc3 vssa vdda pa0 pa1 pa2 vdd pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa15 pa14 vdd vss pa13 pa12 pa11 pa10 pa9 pa8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa3 vss pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 lqfp64 pc13 vdd vss vdd vss pf1-osc_out pc15-osc32_out additional supply pins required for stm32f030rc devices.
pinouts and pin descriptions stm32f030x4/x6/x8/xc 26/93 ds9773 rev 4 figure 6. lqfp48 48-pin package pinout (top view), for stm32f030x4/6/8 devices figure 7. lqfp48 48-pin package pi nout (top view), for stm32f030cc devices 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 lqfp48 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb10 pb11 vss vdd pf7 pf6 pa13 pa12 pa11 pa10 pa9 pa8 pb15 pb14 pb13 pb12 vdd nrst vssa vdda pa0 pa1 pa2 vdd vss pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 pc13 pc14-osc32_in pf0-osc_in pf1-osc_out pc15-osc32_out msv36497v2 io pins replaced by supply pairs for stm32f030cc devices. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 lqfp48 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb10 pb11 vss vdd vdd vss pa13 pa12 pa11 pa10 pa9 pa8 pb15 pb14 pb13 pb12 vdd nrst vssa vdda pa0 pa1 pa2 vdd vss pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 pc13 pc14-osc32_in pf0-osc_in pf1-osc_out pc15-osc32_out msv36484v2 additional supply pins required for stm32f030cc devices.
ds9773 rev 4 27/93 stm32f030x4/x6/x8/xc pinouts and pin descriptions 33 figure 8. lqfp32 32-pin package pinout (top view) figure 9. tssop20 20-pin package pinout (top view) ms32144v1 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 8 910111213 14 15 16 1 2 3 4 5 6 7 lqfp32 pa3 pa4 pa5 pa6 pa7 pb0 pb1 vss pa14 pa13 pa12 pa11 pa10 pa9 pa8 vdd nrst vdda pa0 pa1 pa2 vss boot0 pb7 pb6 pb5 pb4 pb3 pa15 pf0-osc_in pf1-osc_out vdd 21 msv36473v1 1 20 10 11 19 18 17 16 15 12 13 14 2 3 4 5 6 7 8 9 pf0-osc_in boot0 pf1-osc_out nrst vdda pa0 pa9 vdd pa14 pa6 pa7 pb1 vss pa1 pa2 pa3 pa4 pa5 pa13 pa10
pinouts and pin descriptions stm32f030x4/x6/x8/xc 28/93 ds9773 rev 4 table 10. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets belo w the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3 v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers table 11. stm32f030x4/6/8/c pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions 1 1 - - vdd s - - complementary power supply 22-- pc13 i/otc (1) - rtc_tamp1, rtc_ts, rtc_out, wkup2 33-- pc14-osc32_in (pc14) i/o tc (1) - osc32_in 44-- pc15-osc32_out (pc15) i/o tc (1) - osc32_out 5522 pf0-osc_in (pf0) i/o ft - i2c1_sda (5) osc_in 6633 pf1-osc_out (pf1) i/o ft - i2c1_scl (5) osc_out 7 7 4 4 nrst i/o rst - device reset input / internal reset output (active low)
ds9773 rev 4 29/93 stm32f030x4/x6/x8/xc pinouts and pin descriptions 33 8--- pc0 i/otta- eventout, usart6_tx (5) adc_in10 9--- pc1 i/otta- eventout, usart6_rx (5) adc_in11 10 - - - pc2 i/o tta - spi2_miso (5) , eventout adc_in12 11 - - - pc3 i/o tta - spi2_mosi (5) , eventout adc_in13 12 8 - - vssa s - - analog ground 13 9 5 5 vdda s - - analog power supply 14 10 6 6 pa0 i/o tta - usart1_cts (2) , usart2_cts (3)(5) , usart4_tx (5) adc_in0, rtc_tamp2, wkup1 15 11 7 7 pa1 i/o tta - usart1_rts (2) , usart2_rts (3)(5) , eventout, usart4_rx (5) adc_in1 16 12 8 8 pa2 i/o tta - usart1_tx (2) , usart2_tx (3)(5) , tim15_ch1 (3)(5) adc_in2, wkup4 (5) 17 13 9 9 pa3 i/o tta - usart1_rx (2) , usart2_rx (3)(5) , tim15_ch2 (3)(5) adc_in3 18 (4) --- pf4 i/oft (4) eventout - 18 (5) - - - vss s - (5) ground 19 (4) --- pf5 i/oft (4) eventout - 19 (5) --- vdd -- (5) complementary power supply 20 14 10 10 pa4 i/o tta - spi1_nss, usart1_ck (2) usart2_ck (3)(5) , tim14_ch1, usart6_tx (5) adc_in4 21 15 11 11 pa5 i/o tta - spi1_sck, usart6_rx (5) adc_in5 table 11. stm32f030x4/6/8/c pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions
pinouts and pin descriptions stm32f030x4/x6/x8/xc 30/93 ds9773 rev 4 22 16 12 12 pa6 i/o tta - spi1_miso, tim3_ch1, tim1_bkin, tim16_ch1, eventout usart3_cts (5) adc_in6 23 17 13 13 pa7 i/o tta - spi1_mosi, tim3_ch2, tim14_ch1, tim1_ch1n, tim17_ch1, eventout adc_in7 24 - - - pc4 i/o tta - eventout, usart3_tx (5) adc_in14 25 - - - pc5 i/o tta - usart3_rx (5) adc_in15, wkup5 (5) 26 18 14 - pb0 i/o tta - tim3_ch3, tim1_ch2n, eventout, usart3_ck (5) adc_in8 27 19 15 14 pb1 i/o tta - tim3_ch4, tim14_ch1, tim1_ch3n, usart3_rts (5) adc_in9 28 20 - - pb2 i/o ft (6) -- 29 21 - - pb10 i/o ft - spi2_sck (5) , i2c1_scl (2) , i2c2_scl (3)(5) , usart3_tx (5) - 30 22 - - pb11 i/o ft - i2c1_sda (2) , i2c2_sda (3)(5) , eventout, usart3_rx (5) - 31 23 16 - vss s - - ground 32 24 17 16 vdd s - - digital power supply 33 25 - - pb12 i/o ft - spi1_nss (2) , spi2_nss (3)(5) , tim1_bkin, eventout, usart3_ck (5) - table 11. stm32f030x4/6/8/c pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions
ds9773 rev 4 31/93 stm32f030x4/x6/x8/xc pinouts and pin descriptions 33 34 26 - - pb13 i/o ft - spi1_sck (2) , spi2_sck (3)(5) , i2c2_scl (5) , tim1_ch1n, usart3_cts (5) - 35 27 - - pb14 i/o ft - spi1_miso (2) , spi2_miso (3)(5) , i2c2_sda (5) , tim1_ch2n, tim15_ch1 (3)(5) , usart3_rts (5) - 36 28 - - pb15 i/o ft - spi1_mosi (2) , spi2_mosi (3)(5) , tim1_ch3n, tim15_ch1n (3)(5) , tim15_ch2 (3)(5) rtc_refin, wkup7 (5) 37 - - - pc6 i/o ft - tim3_ch1 - 38 - - - pc7 i/o ft - tim3_ch2 - 39 - - - pc8 i/o ft - tim3_ch3 - 40 - - - pc9 i/o ft - tim3_ch4 - 41 29 18 - pa8 i/o ft - usart1_ck, tim1_ch1, eventout, mco - 42 30 19 17 pa9 i/o ft - usart1_tx, tim1_ch2, tim15_bkin (3)(5) i2c1_scl (2)(5) - 43 31 20 18 pa10 i/o ft - usart1_rx, tim1_ch3, tim17_bkin i2c1_sda (2)(5) - 44 32 21 - pa11 i/o ft - usart1_cts, tim1_ch4, eventout, i2c2_scl (5) - 45 33 22 - pa12 i/o ft - usart1_rts, tim1_etr, eventout, i2c2_sda (5) - table 11. stm32f030x4/6/8/c pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions
pinouts and pin descriptions stm32f030x4/x6/x8/xc 32/93 ds9773 rev 4 46 34 23 19 pa13 (swdio) i/o ft (7) ir_out, swdio - 47 (4) 35 (4) -- pf6 i/oft (4) i2c1_scl (2) , i2c2_scl (3) - 47 (5) 35 (5) - - vss s - (5) ground 48 (4) 36 (4) -- pf7 i/oft (4) i2c1_sda (2) , i2c2_sda (3) - 48 (5) 36 (5) -- vdd s- (5) complementary power supply 49 37 24 20 pa14 (swclk) i/o ft (7) usart1_tx (2) , usart2_tx (3)(5) , swclk - 50 38 25 - pa15 i/o ft - spi1_nss, usart1_rx (2) , usart2_rx (3)(5) , usart4_rts (5) , eventout - 51 - - - pc10 i/o ft - usart3_tx (5) , usart4_tx (5) - 52 - - - pc11 i/o ft - usart3_rx (5) , usart4_rx (5) - 53 - - - pc12 i/o ft - usart3_ck (5) , usart4_ck (5) , usart5_tx (5) - 54 - - - pd2 i/o ft - tim3_etr, usart3_rts (5) , usart5_rx (5) - 55 39 26 - pb3 i/o ft - spi1_sck, eventout, usart5_tx (5) - 56 40 27 - pb4 i/o ft - spi1_miso, tim3_ch1, eventout, tim17_bkin (5) , usart5_rx (5) - 57 41 28 - pb5 i/o ft - spi1_mosi, i2c1_smba, tim16_bkin, tim3_ch2, usart5_ck_rts (5) wkup6 (5) table 11. stm32f030x4/6/8/c pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions
ds9773 rev 4 33/93 stm32f030x4/x6/x8/xc pinouts and pin descriptions 33 58 42 29 - pb6 i/o ftf - i2c1_scl, usart1_tx, tim16_ch1n - 59 43 30 - pb7 i/o ftf - i2c1_sda, usart1_rx, tim17_ch1n, usart4_cts (5) - 60 44 31 1 boot0 i b - boot memory selection 61 45 - - pb8 i/o ftf (6) i2c1_scl, tim16_ch1 - 62 46 - - pb9 i/o ftf - i2c1_sda, ir_out, spi2_nss (5) , tim17_ch1, eventout - 63 47 32 15 vss s - - ground 64 48 1 16 vdd s - - digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these gpios must not be used as curr ent sources (e.g. to drive an led). 2. this feature is available on stm 32f030x6 and stm32f030x4 devices only. 3. this feature is availabl e on STM32F030X8 devices only. 4. for stm32f030x4/6/8 devices only. 5. for stm32f030xc devices only. 6. on lqfp32 package, pb2 and pb8 should be treated as unconnec ted pins (even when they are not available on the package, they are not forced to a defined level by hardware). 7. after reset, these pins are configured as swdio and swclk alternate functions, and the internal pull-up on swdio pin and internal pull-down on swclk pin are activated. table 11. stm32f030x4/6/8/c pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions
stm32f030x4/x6/x8/xc 34/93 ds9773 rev 4 table 12. alternate functions selected through gpioa_afr registers for port a pin name af0 af1 af2 af3 af4 af5 af6 pa0 - usart1_cts (2) - - usart4_tx (1) -- usart2_cts (1)(3) pa1 eventout usart1_rts (2) - - usart4_rx (1) tim15_ch1n (1) - usart2_rts (1)(3) pa2 tim15_ch1 (1)(3) usart1_tx (2) -- - - - usart2_tx (1)(3) pa3 tim15_ch2 (1)(3) usart1_rx (2) -- - - - usart2_rx (1)(3) pa4 spi1_nss usart1_ck (2) - - tim14_ch1 usart6_tx (1) - usart2_ck (1)(3) pa5 spi1_sck - - - - usart6_rx (1) - pa6 spi1_miso tim3_ch1 tim1_bkin - usart3_cts (1) tim16_ch1 eventout pa7 spi1_mosi tim3_ch2 tim1_ch1n - tim14_ch1 tim17_ch1 eventout pa8 mco usart1_ck tim1_ch1 eventout - - - pa9 tim15_bkin (1)(3) usart1_tx tim1_ch2 - i2c1_scl (1)(2) mco (1) - pa10 tim17_bkin usart1_rx tim1_ch3 - i2c1_sda (1)(2) -- pa11 eventout usart1_cts tim1_ch4 - - scl -
stm32f030x4/x6/x8/xc ds9773 rev 4 35/93 pa12 eventout usart1_rts tim1_etr - - sda - pa13 swdio ir_out - - - - - pa14 swclk usart1_tx (2) -- - - - usart2_tx (1)(3) pa15 spi1_nss usart1_rx (2) - eventout usart4_rts (1) -- usart2_rx (1)(3) 1. this feature is avail able on stm32f030xc devices. 2. this feature is available on stm32f030x4 and stm32f030x6 devices. 3. this feature is avail able on STM32F030X8 devices. table 13. alternate functions selected through gpiob_afr registers for port b pin name af0 af1 af2 af3 af4 af5 pb0 eventout tim3_ch3 tim1_ch2n - usart3_ck (1) - pb1 tim14_ch1 tim3_ch4 tim1_ch3n - usart3_rts (1) - pb2------ pb3 spi1_sck eventout - - usart5_tx (1) - pb4 spi1_miso tim3_ch1 eventout - usart5_rx (1) tim17_bkin (1) pb5 spi1_mosi tim3_ch2 tim16_ bkin i2c1_smba usart5_ck_rts (1) - pb6 usart1_tx i2c1_scl tim16_ch1n - - - pb7 usart1_rx i2c1_sda tim17_ch1n - usart4_cts (1) - table 12. alternate functions selected thr ough gpioa_afr registers for port a (continued) pin name af0 af1 af2 af3 af4 af5 af6
stm32f030x4/x6/x8/xc 36/93 ds9773 rev 4 pb8 - i2c1_scl tim16_ch1 - - - pb9 ir_out i2c1_sda tim17_ch1 eventout - spi2_nss (1) pb10 - i2c1_scl (2) - - usart3_tx (1) spi2_sck (1) i2c2_scl (1)(3) pb11 eventout i2c1_sda (2) - - usart3_rx (1) - i2c2_sda (1)(3) pb12 spi1_nss (2) eventout tim1_bkin - usart3_rts (1) tim15 (1) spi2_nss (1)(3) pb13 spi1_sck (2) - tim1_ch1n - usart3_cts (1) i2c2_scl (1) spi2_sck (1)(3) pb14 spi1_miso (2) tim15_ch1 (1)(3) tim1_ch2n - usart3_rts (1) i2c2_sda (1) spi2_miso (1)(3) pb15 spi1_mosi (2) tim15_ch2 (1)(3) tim1_ch3n tim15_ch1n (1)(3) -- spi2_mosi (1)(3) 1. this feature is avail able on stm32f030xc devices. 2. this feature is available on stm32f030x4 and stm32f030x6 devices. 3. this feature is avail able on STM32F030X8 devices. table 13. alternate functions selected thr ough gpiob_afr registers for port b (continued) pin name af0 af1 af2 af3 af4 af5
ds9773 rev 4 37/93 stm32f030x4/x6/x8/xc 37 table 14. alternate functions selected through gpioc_afr (1) registers for port c 1. available on stm32f030xc devices only. pin name af0 (2) 2. default alternate functions for stm32f030x4/x6/x8 de vices (they do not have the gpioc_afr registers). af1 (1) af2 (1) pc0 eventout - usart6_tx pc1 eventout - usart6_rx pc2 eventout spi2_miso - pc3 eventout spi2_mosi - pc4 eventout usart3_tx - pc5 - usart3_rx - pc6 tim3_ch1 - - pc7 tim3_ch2 - - pc8 tim3_ch3 - - pc9 tim3_ch4 - - pc10 usart4_tx (1) usart3_tx - pc11 usart4_rx (1) usart3_rx - pc12 usart4_ck (1) usart3_ck usart5_tx pc13--- pc14--- pc15--- table 15. alternate functions selected through gpiod_afr (1) registers for port d 1. available on stm32f030xc devices only. pin name af0 (2) 2. default alternate functions for stm32f030x4/x6/x8 de vices (they do not have the gpiod_afr registers). af1 (1) af2 (1) pd2 tim3_etr usart3_rts usart5_rx table 16. alternate functions selected through gpiof_afr (1) registers for port f 1. available on stm32f030xc devices only. pin name af0 (2) 2. default alternate functions for stm32f030x4/x6/x8 de vices (they do not have the gpiof_afr registers). af1 (1) pf0 - i2c1_sda pf1 - i2c1_scl pf4 eventout (1) pf5 eventout (1) pf6 i2c1_scl (3) , i2c2_scl (4) 3. applies to stm32f030x4/x6 4. applies to STM32F030X8 pf7 i2c1_sda (3) , i2c2_sda (4)
memory mapping stm 32f030x4/x6/x8/xc 38/93 ds9773 rev 4 5 memory mapping figure 10. stm32f030x4/x6/x8/xc memory map 1. the start address of the system memory is 0x1fff ec 00 for stm32f030x4, stm32f030x6 and STM32F030X8 devices, and 0x1fff d800 for stm32f030xc devices. msv36474v2 ahb2 0 1 2 3 4 5 6 7 0xffff ffff peripherals sram flash memory reserved system memory option bytes 0xe010 0000 flash, system memory or sram, depending on boot configuration 0x0000 0000 0xe000 0000 0xc000 0000 0xa000 0000 0x8000 0000 0x6000 0000 0x4000 0000 0x2000 0000 0x0000 0000 0x0800 0000 0x0804 0000 0x1fff xx00 (1) 0x1fff f800 0x1fff ffff 0x0004 0000 reserved code apb apb reserved 0x4000 0000 0x4000 8000 0x4001 0000 0x4001 8000 reserved 0x4002 0000 ahb1 0x4800 0000 reserved 0x4800 17ff 0x4002 43ff cortex-m0 internal peripherals reserved 0x1fff fc00 reserved reserved reserved reserved reserved reserved reserved
ds9773 rev 4 39/93 stm32f030x4/x6/x8/xc memory mapping 40 table 17. stm32f030x4/x6/x8/xc peri pheral register boundary addresses bus boundary address size peripheral - 0x4800 1800 - 0x5fff ffff ~384 mb reserved ahb2 0x4800 1400 - 0x4800 17ff 1 kb gpiof 0x4800 1000 - 0x4800 13ff 1 kb reserved 0x4800 0c00 - 0x4800 0fff 1 kb gpiod 0x4800 0800 - 0x4800 0bff 1 kb gpioc 0x4800 0400 - 0x4800 07ff 1 kb gpiob 0x4800 0000 - 0x4800 03ff 1 kb gpioa - 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 3400 - 0x4002 43ff 4 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash interface 0x4002 1400 - 0x4002 1fff 3 kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0400 - 0x4002 0fff 3 kb reserved 0x4002 0000 - 0x4002 03ff 1 kb dma - 0x4001 8000 - 0x4001 ffff 32 kb reserved apb 0x4001 5c00 - 0x4001 7fff 9 kb reserved 0x4001 5800 - 0x4001 5bff 1 kb dbgmcu 0x4001 4c00 - 0x4001 57ff 3 kb reserved 0x4001 4800 - 0x4001 4bff 1 kb tim17 0x4001 4400 - 0x4001 47ff 1 kb tim16 0x4001 4000 - 0x4001 43ff 1 kb tim15 (1) 0x4001 3c00 - 0x4001 3fff 1 kb reserved 0x4001 3800 - 0x4001 3bff 1 kb usart1 0x4001 3400 - 0x4001 37ff 1 kb reserved 0x4001 3000 - 0x4001 33ff 1 kb spi1 0x4001 2c00 - 0x4001 2fff 1 kb tim1 0x4001 2800 - 0x4001 2bff 1 kb reserved 0x4001 2400 - 0x4001 27ff 1 kb adc 0x4001 1800 - 0x4001 23ff 3 kb reserved 0x4001 1400 - 0x4001 17ff 1 kb usart6 (2) 0x4001 0800 - 0x4001 13ff 3 kb reserved 0x4001 0400 - 0x4001 07ff 1 kb exti 0x4001 0000 - 0x4001 03ff 1 kb syscfg
memory mapping stm 32f030x4/x6/x8/xc 40/93 ds9773 rev 4 - 0x4000 8000 - 0x4000 ffff 32 kb reserved apb 0x4000 7400 - 0x4000 7fff 3 kb reserved 0x4000 7000 - 0x4000 73ff 1 kb pwr 0x4000 5c00 - 0x4000 6fff 5 kb reserved 0x4000 5800 - 0x4000 5bff 1 kb i2c2 (1) 0x4000 5400 - 0x4000 57ff 1 kb i2c1 0x4000 5000 - 0x4000 53ff 1 kb usart5 (2) 0x4000 4c00 - 0x4000 4fff 1 kb usart4 (2) 0x4000 4800 - 0x4000 4bff 1 kb usart3 (2) 0x4000 4400 - 0x4000 47ff 1 kb usart2 (1) 0x4000 3c00 - 0x4000 43ff 2 kb reserved 0x4000 3800 - 0x4000 3bff 1 kb spi2 (1) 0x4000 3400 - 0x4000 37ff 1 kb reserved 0x4000 3000 - 0x4000 33ff 1 kb iwdg 0x4000 2c00 - 0x4000 2fff 1 kb wwdg 0x4000 2800 - 0x4000 2bff 1 kb rtc 0x4000 2400 - 0x4000 27ff 1 kb reserved 0x4000 2000 - 0x4000 23ff 1 kb tim14 0x4000 1800 - 0x4000 1fff 2 kb reserved 0x4000 1400 - 0x4000 17ff 1 kb tim7 (2) 0x4000 1000 - 0x4000 13ff 1 kb tim6 (1) 0x4000 0800 - 0x4000 0fff 2 kb reserved 0x4000 0400 - 0x4000 07ff 1 kb tim3 0x4000 0000 - 0x4000 03ff 1 kb reserved 1. this feature is available on STM32F030X8 and stm32f030xc devices only. for stm32f030x6 and stm32f060x4, the area is reserved. 2. this feature is available on st m32f030xc devices only. this area is reserved for stm32f030x4/6/8 devices. table 17. stm32f030x4/x6/x8/xc peripheral register boundary addresses (continued) bus boundary address size peripheral
ds9773 rev 4 41/93 stm32f030x4/x6/x8/xc electrical characteristics 75 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, a ll voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply vo ltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desig n simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum valu es refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by ch aracterization of a batch of samples from a standard diffusion lot over the full temperat ure range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 11 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 12 . figure 11. pin loading conditi ons figure 12. pin input voltage ms19210v1 mcu pin c = 50 pf ms19211v1 mcu pin v in
electrical characteristics stm32f030x4/x6/x8/xc 42/93 ds9773 rev 4 6.1.6 power supply scheme figure 13. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 6.1.7 current consumption measurement figure 14. current consum ption measurement scheme msv39025v1 v dd level shifter io logic kernel logic (cpu, digital & memories) lse, rtc, wake-up logic in out regulator gpios 2 x 100 nf +1 x 4.7 f 2 x v ss 2 x v dd v core power switch v ddio1 adc analog: (rcs, pll, ) v ref+ v ref- v dda 10 nf +1 f v dda v ssa ms32142v2 v dd v dda i dd i dda
ds9773 rev 4 43/93 stm32f030x4/x6/x8/xc electrical characteristics 75 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 18: voltage characteristics , table 19: current characteristics and table 20: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 18. voltage characteristics (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. symbol ratings min max unit v dd ?v ss external main supply voltage -0.3 4.0 v v dda ?v ss external analog supply voltage -0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda -0.4v v in (2) 2. v in maximum must always be respected. refer to table 19: current characteristics for the maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v ddiox + 4.0 (3) 3. v ddiox is internally c onnected with vdd pin. v input voltage on tta pins v ss ? 0.3 4.0 v boot0 0 v ddiox + 4.0 (3) v input voltage on any other pin v ss ? 0.3 4.0 v | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins -50mv v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics -
electrical characteristics stm32f030x4/x6/x8/xc 44/93 ds9773 rev 4 6.3 operating conditions 6.3.1 general operating conditions table 19. current characteristics symbol ratings max. unit i vdd total current into sum of all vdd power lines (source) (1) 120 ma i vss total current out of sum of all vss ground lines (sink) (1) -120 i vdd(pin) maximum current into each vdd power pin (source) (1) 100 i vss(pin) maximum current out of each vss ground pin (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin -25 i io(pin) total output current sunk by sum of all i/os and control pins (2) 80 total output current sourced by su m of all i/os and control pins (2) -80 i inj(pin) (3) injected current on ft and ftf pins -5/+0 (4) injected current on tc and rst pin 5 injected current on tta pins (5) 5 i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (vdd, vdda) and ground (vss, vssa) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two c onsecutive power supply pins referr ing to high pin count qfp packages. 3. a positive injecti on is induced by v in > v ddiox while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 18: voltage characteristics for the maximum allowed input voltage values. 4. positive injection is not possible on these i/os and does not occur for input vo ltages lower than the specified maximum value. 5. on these i/os, a positive injection is induced by v in > v dda . negative injection disturbs the analog performance of the device. see note (2) below table 52: adc accuracy . 6. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 20. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c table 21. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 48 mhz f pclk internal apb clock frequency - 0 48 v dd standard operating voltage - 2.4 3.6 v
ds9773 rev 4 45/93 stm32f030x4/x6/x8/xc electrical characteristics 75 6.3.2 operating conditions at power-up / power-down the parameters given in table 22 are derived from tests performed under the ambient temperature condition summarized in table 21 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 23 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . v dda analog operating voltage must have a potential equal to or higher than v dd 2.4 3.6 v v in i/o input voltage tc and rst i/o -0.3 v ddiox +0.3 v tta i/o -0.3 v dda +0.3 (2) ft and ftf i/o -0.3 5.5 (2) boot0 0 5.5 p d power dissipation at t a = 85 c for suffix 6 (1) lqfp64 - 455 mw lqfp48 - 364 lqfp32 - 357 tssop20 - 263 t a ambient temperature for the suffix 6 version maximum power dissipation -40 85 c low power dissipation (2) -40 105 t j junction temperature range suffix 6 version -40 105 c 1. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 2. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.5: thermal characteristics ). table 21. general operating conditions (continued) symbol parameter conditions min max unit table 22. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate - 0 s/v v dd fall time rate 20 t vdda v dda rise time rate - 0 v dda fall time rate 20 table 23. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) power on/power down reset threshold falling edge (2) 1.80 1.88 1.96 (3) v rising edge 1.84 (3) 1.92 2.00 v
electrical characteristics stm32f030x4/x6/x8/xc 46/93 ds9773 rev 4 6.3.4 embedded reference voltage the parameters given in table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . 6.3.5 supply current characteristics the current consumption is a function of se veral parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 14: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. v pdrhyst pdr hysteresis - - 40 - mv t rsttempo (4) reset temporization - 1.50 2.50 4.50 ms 1. the pdr detector monitors v dd and also v dda (if kept enabled in the option bytes). the por detector monitors only v dd . 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 3. data based on characterization results, not tested in production. 4. guaranteed by design, not tested in production. table 23. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit table 24. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage -40c < t a < +85c 1.2 1.23 1.25 v t start adc_in17 buffer startup time ---10 (1) s t s_vrefint adc sampling time when reading the internal reference voltage - 4 (1) --s v refint internal reference voltage spread over the temperature range v dda = 3 v - - 10 (1) 1. guaranteed by design, not tested in production. mv t coeff temperature coefficient - -100 (1) - 100 (1) ppm/c
ds9773 rev 4 47/93 stm32f030x4/x6/x8/xc electrical characteristics 75 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input mode ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled f pclk = f hclk the parameters given in table 25 to table 27 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . table 25. typical and maximum current consumption from v dd supply at v dd = 3.6 v (1) symbol parameter conditions f hclk all peripherals enabled unit typ max @ t a (2) 85 c i dd supply current in run mode, code executing from flash hsi or hse clock, pll on 48 mhz 22.0 22.8 ma 48 mhz 26.8 30.2 24 mhz 12.2 13.2 24 mhz 14.1 16.2 hsi or hse clock, pll off 8 mhz 4.4 5.2 8 mhz 4.9 5.6 i dd supply current in run mode, code executing from ram hsi or hse clock, pll on 48 mhz 22.2 23.2 ma 48 mhz 26.1 29.3 24 mhz 11.2 12.2 24 mhz 13.3 15.7 hsi or hse clock, pll off 8 mhz 4.0 4.5 8 mhz 4.6 5.2 i dd supply current in sleep mode, code executing from flash or ram hsi or hse clock, pll on 48 mhz 14 15.3 ma 48 mhz 17.0 19.0 24 mhz 7.3 7.8 24 mhz 8.7 10.1 hsi or hse clock, pll off 8 mhz 2.6 2.9 8 mhz 3.0 3.5 1. the gray shading is used to distingu ish the values for stm32f030xc devices. 2. data based on characterization results, not te sted in production unless otherwise specified.
electrical characteristics stm32f030x4/x6/x8/xc 48/93 ds9773 rev 4 table 26. typical and maximum current consumption from the v dda supply (1) symbol parameter conditions (2) f hclk v dda = 3.6 v unit typ max @ t a (3) 85 c i dda supply current in run or sleep mode, code executing from flash memory or ram hse bypass, pll on 48 mhz 175 215 a 48 mhz 160 192 hse bypass, pll off 8 mhz 3.9 4.9 8 mhz 3.7 4.6 1 mhz 3.9 4.1 1 mhz 3.3 4.4 hsi clock, pll on 48 mhz 244 275 48 mhz 235 275 hsi clock, pll off 8 mhz 85 105 8 mhz 77 92 1. the gray shading is used to distingui sh the values for stm32f030xc devices. 2. current consumption from the v dda supply is independent of whether the digita l peripherals are enabled or disabled, being in run or sleep mode or executing from flash or ram. furthermore, when the pll is off, i dda is independent of the frequency. 3. data based on characterization results, not tested in production.
ds9773 rev 4 49/93 stm32f030x4/x6/x8/xc electrical characteristics 75 typical current consumption the mcu is placed under the following conditions: ? v dd = v dda = 3.3 v ? all i/o pins are in analog input configuration ? the flash access time is adjusted to f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled, f pclk = f hclk ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8 and 16 is used for the frequencies 4 mhz, 2 mhz, 1 mhz and 500 khz respectively table 27. typical and maximum consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda ) max (1) unit 3.6 v t a = 85 c i dd supply current in stop mode regulator in run mode, all oscillators off 19 48 a regulator in low-power mode, all oscillators off 5 32 supply current in standby mode lsi on and iwdg on 2 - i dda supply current in stop mode v dda monitoring on regulator in run or low- power mode, all oscillators off 2.9 3.5 supply current in standby mode lsi on and iwdg on 3.3 - lsi off and iwdg off 2.8 3.5 supply current in stop mode v dda monitoring off regulator in run or low- power mode, all oscillators off 1.7 - supply current in standby mode lsi on and iwdg on 2.3 - lsi off and iwdg off 1.4 - 1. data based on characterization results, not tested in production unless otherwise specified.
electrical characteristics stm32f030x4/x6/x8/xc 50/93 ds9773 rev 4 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low. the value of this curren t consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 46: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally app lied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the inpu t value. unless this specific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably th e case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral curren t consumption measured previously, the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the i/o supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: table 28. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 48 mhz 23.3 11.5 ma 8 mhz 4.5 3.0 i dda supply current in run mode from v dda supply 48 mhz 158 158 a 8 mhz 2.43 2.43 i sw v ddiox f sw c =
ds9773 rev 4 51/93 stm32f030x4/x6/x8/xc electrical characteristics 75 where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v ddiox is the i/o supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacita nce including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 6.3.6 wakeup time from low-power mode the wakeup times given in table 30 are the latency between the event and the execution of the first user instruction. the device goes in low-power mode after the wfe (wait for event) instruction, in the case of a wfi (wai t for interruption) inst ruction, 16 cpu cycles must be added to the following timings due to the interrupt latency in the cortex m0 architecture. the sysclk clock source setti ng is kept unchanged afte r wakeup from sleep mode. during wakeup from stop or standby mode, sysclk takes the default setting: hsi 8 mhz. the wakeup source from sleep and stop mode is an exti line configured in event mode. the wakeup source from standby mode is the wkup1 pin (pa0). all timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . table 29. switching output i/o current consumption symbol parameter conditions (1) 1. c s = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v ddiox = 3.3 v c ext = 0 pf c = c int + c ext + c s 4 mhz 0.18 ma 8 mhz 0.37 16 mhz 0.76 24 mhz 1.39 48 mhz 2.188 v ddiox = 3.3 v c ext = 22 pf c = c int + c ext + c s 4 mhz 0.49 8 mhz 0.94 16 mhz 2.38 24 mhz 3.99 v ddiox = 3.3 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.81 8 mhz 1.7 16 mhz 3.67
electrical characteristics stm32f030x4/x6/x8/xc 52/93 ds9773 rev 4 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscilla tor is switched off and the in put pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 15: high-speed external clock source ac timing diagram . figure 15. high-speed external clock source ac timing diagram table 30. low-power mode wakeup timings symbol parameter conditions typ @v dd = v dda max unit = 3.3 v t wustop wakeup from stop mode regulator in run mode 2.8 5 s t wustandby wakeup from standby mode - 51 - t wusleep wakeup from sleep mode - 4 sysclk cycles - table 31. high-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. min typ max unit f hse_ext user external clock source frequency 1 8 32 mhz v hseh osc_in input pin high level voltage 0.7 v ddiox -v ddiox v v hsel osc_in input pin low level voltage v ss - 0.3 v ddiox t w(hseh) t w(hsel) osc_in high or low time 15 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 ms19214v2 v hseh t f(hse) 90% 10% t hse t t r(hse) v hsel t w(hseh) t w(hsel)
ds9773 rev 4 53/93 stm32f030x4/x6/x8/xc electrical characteristics 75 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 16 . figure 16. low-speed external cl ock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are base d on design simulation results obtained with typical external components specified in table 33 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufa cturer for more details on the resonator characteristics (frequency, package, accuracy). table 32. low-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. min typ max unit f lse_ext user external clock source frequency - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7 v ddiox -v ddiox v v lsel osc32_in input pin low level voltage v ss - 0.3 v ddiox t w(lseh) t w(lsel) osc32_in high or low time 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 50 table 33. hse oscilla tor characteristics symbol parameter conditions (1) min (2) typ max (2) unit f osc_in oscillator frequency - 4 8 32 mhz r f feedback resistor - - 200 - k ms19215v2 v lseh t f(lse) 90% 10% t lse t t r(lse) v lsel t w(lseh) t w(lsel)
electrical characteristics stm32f030x4/x6/x8/xc 54/93 ds9773 rev 4 for c l1 and c l2 , it is recommended to use high-qualit y external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 17 ). c l1 and c l2 are usually the same size. the crystal manufac turer typically specifies a lo ad capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selectin g the crystal, refer to the ap plication note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 17. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the info rmation given in this paragraph ar e based on design simulation results i dd hse current consumption during startup (3) --8.5 ma v dd = 3.3 v, rm = 45 , cl = 10 pf@8 mhz -0.5- v dd = 3.3 v, rm = 30 , cl = 20 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) startup time v dd is stabilized - 2 - ms 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. guaranteed by design, not tested in production. 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal res onator and it can vary significantly with the crystal manufacturer table 33. hse oscilla tor characteristics symbol parameter conditions (1) min (2) typ max (2) unit ms19876v1 (1) osc_in osc_out r f bias controlled gain f hse r ext 8 mhz resonator resonator with integrated capacitors c l1 c l2
ds9773 rev 4 55/93 stm32f030x4/x6/x8/xc electrical characteristics 75 obtained with typical external components specified in table 34 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time . refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for information on selectin g the crystal, refer to the ap plication note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 18. typical application with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. table 34. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. min (2) typ max (2) 2. guaranteed by design, not tested in production. unit i dd lse current consumption low drive capability - 0.5 0.9 a medium-low drive capability - - 1 medium-high drive capability - - 1.3 high drive capability - - 1.6 g m oscillator transconductance low drive capability 5 - - a/v medium-low drive capability 8 - - medium-high drive capability 15 - - high drive capability 25 - - t su(lse) (3) 3. t su(lse) is the startup time measured from the mom ent it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. th is value is measured for a standard cr ystal and it can vary significantly with the crystal manufacturer startup time v ddiox is stabilized - 2 - s ms30253v2 osc32_in osc32_out drive programmable amplifier f lse 32.768 khz resonator resonator with integrated capacitors c l1 c l2
electrical characteristics stm32f030x4/x6/x8/xc 56/93 ds9773 rev 4 6.3.8 internal clock source characteristics the parameters given in table 35 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi) rc oscillator high-speed internal 14 mhz (hsi14) rc oscillator (dedicated to adc) low-speed internal (lsi) rc oscillator table 35. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = -40 to 85c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 8 - mhz trim hsi user trimming step - - - 1 (2) 2. guaranteed by design, not tested in production. % ducy hsi duty cycle - 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = -40 to 85c - 5 - % t a = 25c - 1 (3) 3. with user calibration. -% t su(hsi) hsi oscillator startup time - 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption --80-a table 36. hsi14 oscillator characteristics (1) 1. v dda = 3.3 v, t a = -40 to 85 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi14 frequency - - 14 - mhz trim hsi14 user-trimming step - - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi14) duty cycle - 45 (2) -55 (2) % acc hsi14 accuracy of the hsi14 oscillator (factory calibrated) t a = ?40 to 85 c - 5 - % t su(hsi14) hsi14 oscillator startup time - 1 (2) -2 (2) s i dda(hsi14) hsi14 oscillator power consumption - - 100 - a table 37. lsi oscillator characteristics (1) symbol parameter min typ max unit f lsi frequency 30 40 50 khz
ds9773 rev 4 57/93 stm32f030x4/x6/x8/xc electrical characteristics 75 6.3.9 pll characteristics the parameters given in table 38 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . 6.3.10 memory characteristics flash memory the characteristics are given at t a = -40 to 85 c unless otherwise specified. t su(lsi) (2) lsi oscillator startup time - - 85 s i dda(lsi) (2) lsi oscillator power consumption - 0.75 - a 1. v dda = 3.3 v, t a = -40 to 85 c unless otherwise specified. 2. guaranteed by design, not tested in production. table 37. lsi oscillator characteristics (1) symbol parameter min typ max unit table 38. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care to use the appropriate multiplier factors to obtain pll input clock values compatible with the range defined by f pll_out . 1 (2) 8.0 24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -48mhz t lock pll lock time - - 200 (2) 2. guaranteed by design, not tested in production. s jitter pll cycle-to-cycle jitter - - 300 (2) ps table 39. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = -40 to +85 c - 53.5 - s t erase page erase time (2) 2. page size is 1kb for stm32f030x4/6/ 8 devices and 2kb for stm32f030xc devices t a = -40 to +85 c - 30 - ms t me mass erase time t a = -40 to +85 c - 30 - ms i dd supply current write mode - - 10 ma erase mode - - 12 ma v prog programming voltage - 2.4 - 3.6 v
electrical characteristics stm32f030x4/x6/x8/xc 58/93 ds9773 rev 4 6.3.11 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 41 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu so ftware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the us er applies emc software optimization and prequalification tests in re lation with the emc level requ ested for his application. software recommendations table 40. flash memory endurance and data retention symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. unit n end endurance t a = -40 to +85 c 1 kcycle t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 20 years table 41. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3v, lqfp48, t a = +25 c, f hclk = 48 mhz, conforming to iec 61000-4-2 3b (1) 2b (2) 1. applies to stm32f030xc. 2. applies to stm32f030x4/x6/x8. v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3v, lqfp48, t a = +25c, f hclk = 48 mhz, conforming to iec 61000-4-4 4b
ds9773 rev 4 59/93 stm32f030x4/x6/x8/xc electrical characteristics 75 the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forc ing a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when une xpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement me thods, the device is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a n egative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the devi ce (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 42. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz s emi peak level v dd = 3.6 v, t a = 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz -3 dbv 30 to 130 mhz 23 130 mhz to 1 ghz 17 emi level 4 -
electrical characteristics stm32f030x4/x6/x8/xc 60/93 ds9773 rev 4 static latch-up two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with ei a/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v ddiox (for standard, 3.3 v-capable i/o pi ns) should be avoided during normal product operation. however, in order to gi ve an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of the -5 a/+0 a range) or other functional failure (for example reset occurrence or oscillator freque ncy deviation). the characterization results are given in table 45 . negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. table 43. esd absolute maximum ratings symbol ratings conditions packages class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 all 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 all c4 (2) c3 (3) 500 (2) 250 (3) v 1. data based on characterization results, not tested in production. 2. applicable to stm32f030xc 3. applicable to stm32f030x4, stm32f030x6, and STM32F030X8 table 44. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a
ds9773 rev 4 61/93 stm32f030x4/x6/x8/xc electrical characteristics 75 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 46 are derived from tests performed under the conditions summarized in table 21: general operating conditions . all i/os are designed as cmos- and ttl-compliant (except boot0). table 45. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 and pf1 pins -0 na ma injected current on pa9, pb3, pb13, pf11 pins with induced leakage current on adjacent pins less than 50 a -5 na injected current on pa11 and pa12 pins with induced leakage current on adjacent pins less than -1 ma -5 na injected current on all other ft and ftf pins -5 na injected current on pb0 and pb1 pins -5 na injected current on pc0 pin -0 +5 injected current on all other tta, tc and rst pins -5 +5 table 46. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v ddiox +0.07 (1) v ft and ftf i/o - - 0.475 v ddiox ?0.2 (1) boot0 - - 0.3 v ddiox ?0.3 (1) all i/os except boot0 pin --0.3 v ddiox v ih high level input voltage tc and tta i/o 0.445 v ddiox +0.398 (1) -- v ft and ftf i/o 0.5 v ddiox +0.2 (1) -- boot0 0.2 v ddiox +0.95 (1) -- all i/os except boot0 pin 0.7 v ddiox -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) -
electrical characteristics stm32f030x4/x6/x8/xc 62/93 ds9773 rev 4 all i/os are cmos- and ttl-compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 19 for standard i/os, and in figure 20 for 5 v tolerant i/os. the following curves are design simulation results, not tested in production. i lkg input leakage current (2) tc, ft and ftf i/o tta in digital mode v ss v in v ddiox -- 0.1 a tta in digital mode v ddiox v in v dda --1 tta in analog mode v ss v in v dda -- 0.2 ft and ftf i/o (3) v ddiox v in 5 v --10 r pu weak pull-up equivalent resistor (4) v in = v ss 25 40 55 k r pd weak pull-down equivalent resistor (4) v in = v ddiox 25 40 55 k c io i/o pin capacitance - - 5 - pf 1. data based on design simulation only. not tested in production. 2. the leakage could be higher than the maximum value, if negative current is injected on adjacent pins. refer to table 45: i/o current injection susceptibility . 3. to sustain a voltage higher than v ddiox + 0.3 v, the internal pull-up/pull -down resistors must be disabled. 4. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimal (~10% order). table 46. i/o static characteristics (continued) symbol parameter conditions min typ max unit
ds9773 rev 4 63/93 stm32f030x4/x6/x8/xc electrical characteristics 75 figure 19. tc and tta i/o input characteristics figure 20. five volt tolerant (ft and ftf) i/o input characteristics msv32130v4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 0.5 1 1.5 2 2.5 3 tested range tested range v ihmin = 0.7 v ddiox (cmos standard requirement) v ilmax = 0.3 v ddiox (cmos standard requirement) undefined input range v ihmin = 0.445 v ddiox + 0.398 v ilmax = 0.3 v ddiox + 0.07 v in (v) v ddiox (v) ttl standard requirement ttl standard requirement msv32131v4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 0.5 1 1.5 2 2.5 3 tested range tested range v ihmin = 0.7 v ddiox (cmos standard requirement) v ilmax = 0.3 v ddiox (cmos standard requirement) undefined input range v ihmin = 0.5 v ddiox + 0.2 v ilmax = 0.475 v ddiox - 0.2 v in (v) v ddiox (v) ttl standard requirement ttl standard requirement
electrical characteristics stm32f030x4/x6/x8/xc 64/93 ds9773 rev 4 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v ddiox, plus the maximum consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 18: voltage characteristics ). ? the sum of the currents sunk by all the i/os on v ss , plus the maximum consumption of the mcu sunk on v ss , cannot exceed the absolute maximum rating i vss (see table 18: voltage characteristics ). output voltage levels unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . all i/os are cmos- and ttl-compliant (ft, tta or tc unless otherwise specified). input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 21 and table 48 , respectively. unless otherwise specified, th e parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . table 47. output voltage characteristics (1) symbol parameter conditions min max unit v ol output low level voltage for an i/o pin |i io | = 8 ma v ddiox 2.7 v -0.4 v v oh output high level voltage for an i/o pin v ddiox ?0.4 - v ol (2) output low level voltage for an i/o pin |i io | = 20 ma v ddiox 2.7 v -1.3 v v oh (2) output high level voltage for an i/o pin v ddiox ?1.3 - v ol (2) output low level voltage for an i/o pin |i io | = 6 ma -0.4 v v oh (2) output high level voltage for an i/o pin v ddiox ?0.4 - v olfm+ (2) output low level voltage for an ftf i/o pin in fm+ mode |i io | = 20 ma v ddiox 2.7 v -0.4v |i io | = 10 ma - 0.4 v 1. the i io current sourced or sunk by the device must alwa ys respect the absolute maxi mum rating specified in table 18: voltage characteristics , and the sum of the currents sourced or sunk by all the i/o s (i/o ports and control pins) must always respect the absolute maximum ratings i io . 2. data based on characterization results. not tested in production.
ds9773 rev 4 65/93 stm32f030x4/x6/x8/xc electrical characteristics 75 table 48. i/o ac characteristics (1)(2) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox 2.4 v -2mhz t f(io)out output fall time - 125 ns t r(io)out output rise time - 125 01 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox 2.4 v -10mhz t f(io)out output fall time - 25 ns t r(io)out output rise time - 25 11 f max(io)out maximum frequency (3) c l = 30 pf, v ddiox 2.7 v - 50 mhz c l = 50 pf, v ddiox 2.7 v - 30 c l = 50 pf, 2.4 v v ddiox < 2.7 v - 20 t f(io)out output fall time c l = 30 pf, v ddiox 2.7 v - 5 ns c l = 50 pf, v ddiox 2.7 v - 8 c l = 50 pf, 2.4 v v ddiox < 2.7 v - 12 t r(io)out output rise time c l = 30 pf, v ddiox 2.7 v - 5 c l = 50 pf, v ddiox 2.7 v - 8 c l = 50 pf, 2.4 v v ddiox < 2.7 v - 12 fm+ configuration (4) f max(io)out maximum frequency (3) c l = 50 pf, v ddiox 2.4 v -2mhz t f(io)out output fall time - 12 ns t r(io)out output rise time - 34 -t extipw pulse width of external signals detected by the exti controller -10-ns 1. the i/o speed is configured using the ospeedrx[1:0] bits . refer to the stm32f0xxxx rm0360 reference manual for a description of gpio port configuration register. 2. guaranteed by design, not tested in production. 3. the maximum frequency is defined in figure 21 . 4. when fm+ configuration is set, the i/o speed control is bypassed. refer to the stm32f0xxxx reference manual rm0360 for a detailed description of fm+ i/o configuration.
electrical characteristics stm32f030x4/x6/x8/xc 66/93 ds9773 rev 4 figure 21. i/o ac characteristics definition 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu . unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 21: general operating conditions . ms32132v3 t 10% 50% 90% 10% 50% 90% maximum frequency is achieved if (t + t ) when loaded by c (see the table i/o ac characteristics definition ) rf r(io)out t f(io)out t l 2 3 t and if the duty cycle is (45-55%) table 49. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage - - - 0.3 v dd +0.07 (1) v v ih(nrst) nrst input high level voltage - 0.445 v dd +0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis --200-mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k v f(nrst) nrst input filtered pulse - - - 100 (1) ns v nf(nrst) nrst input not filtered pulse 2.7 < v dd < 3.6 300 (3) -- ns 2.4 < v dd < 3.6 500 (3) -- 1. data based on design simulation only. not tested in production. 2. the pull-up is designed with a true re sistance in series with a switchable pmos . this pmos contribution to the series resistance is minimal (~10% order). 3. data based on design simulation only. not tested in production.
ds9773 rev 4 67/93 stm32f030x4/x6/x8/xc electrical characteristics 75 figure 22. recommended nrst pin protection 1. the external capacitor protects the device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 49: nrst pin characteristics . otherwise the reset will not be taken into account by the device. 6.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in table 50 are preliminary values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions su mmarized in table 21: general operating conditions . note: it is recommended to perform a calibration after each power-up. ms19878v4 r pu v dd internal reset external reset circuit (1) nrst (2) filter 0.1 f (3) table 50. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on - 2.4 - 3.6 v i dda (adc) current consumption of the adc (1) v dd = v dda = 3.3 v - 0.9 - ma f adc adc clock frequency - 0.6 - 14 mhz f s (2) sampling rate - 0.05 - 1 mhz f trig (2) external trigger frequency f adc = 14 mhz - - 823 khz ---171/f adc v ain conversion voltage range - 0 - v dda v r ain (2) external input impedance see equation 1 and table 51 for details --50k r adc (2) sampling switch resistance ---1k c adc (2) internal sample and hold capacitor ---8pf
electrical characteristics stm32f030x4/x6/x8/xc 68/93 ds9773 rev 4 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). t cal (2)(3) calibration time f adc = 14 mhz 5.9 s -831/f adc w latency (2)(4) adc_dr register write latency adc clock = hsi14 1.5 adc cycles + 2 f pclk cycles - 1.5 adc cycles + 3 f pclk cycles - adc clock = pclk/2 - 4.5 - f pclk cycle adc clock = pclk/4 - 8.5 - f pclk cycle t latr (2) trigger conversion latency f adc = f pclk /2 = 14 mhz 0.196 s f adc = f pclk /2 5.5 1/f pclk f adc = f pclk /4 = 12 mhz 0.219 s f adc = f pclk /4 10.5 1/f pclk f adc = f hsi14 = 14 mhz 0.188 - 0.259 s jitter adc adc jitter on trigger conversion f adc = f hsi14 -1-1/f hsi14 t s (2) sampling time f adc = 14 mhz 0.107 - 17.1 s - 1.5 - 239.5 1/f adc t stab (2) stabilization time - 14 1/f adc t conv (2) total conversion time (including sampling time) f adc = 14 mhz, 12-bit resolution 1 - 18 s 12-bit resolution 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. during conversion of the sampled value (12.5 x a dc clock period), an additional consumption of 100 a on i dda and 60 a on i dd should be taken into account. 2. guaranteed by design, not tested in production. 3. specified value includes only a dc timing. it does not include the latency of the register access. 4. this parameter specify latency for transfe r of the conversion result to the adc_dr register. eoc flag is set at this time. table 50. adc characteristics (continued) symbol parameter conditions min typ max unit r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? <
ds9773 rev 4 69/93 stm32f030x4/x6/x8/xc electrical characteristics 75 table 51. r ain max for f adc = 14 mhz t s (cycles) t s (s) r ain max (k ) (1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.52.0425.2 41.52.9637.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na 1. guaranteed by design, not tested in production. table 52. adc accuracy (1)(2)(3) symbol parameter test conditions typ max (4) unit et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k v dda = 2.7 v to 3.6 v t a = ? 40 to 85 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting n egative current on any of the standard (non-robust) analog input pins should be avoided as this signific antly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production.
electrical characteristics stm32f030x4/x6/x8/xc 70/93 ds9773 rev 4 figure 23. adc accuracy characteristics figure 24. typical connection diagram using the adc 1. refer to table 50: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 13: power supply scheme . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. e t = total unajusted error : maximum deviation between the actual and ideal transfer curves. e o = offset error : maximum deviation between the first actual transition and the first ideal one. e g = gain error : deviation between the last ideal transition and the last actual one. e d = differential linearity error : maximum deviation between actual steps and the ideal ones. e l = integral linearity error : maximum deviation between any actual transition and the end point correlation line. (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line 4095 4094 4093 7 6 5 4 3 2 1 0 23456 1 7 4093 4094 4095 4096 v dda v ssa e o e t e l e g e d 1 lsb ideal (1) (3) (2) ms19880v2 ms33900v1 v dda ainx i l 1 a v t r ain (1) c par asitic v ain v t r adc 12-bit con ver ter c adc sample and hold adc con ver ter
ds9773 rev 4 71/93 stm32f030x4/x6/x8/xc electrical characteristics 75 6.3.17 temperature sensor characteristics 6.3.18 timer characteristics the parameters given in the following tables are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, in put capture, external clock, pwm output). table 53. ts characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 30 voltage at 30 c ( 5 c) (2) 1.34 1.43 1.52 v t start (1) adc_in16 buffer startup time - - 10 s t s_temp (1) adc sampling time when reading the temperature 4- -s 1. guaranteed by design, not tested in production. 2. measured at v dda = 3.3 v 10 mv. the v 30 adc conversion result is stored in the ts_cal1 byte . refer to table 3: temperature sensor calibration values . table 54. timx characteristics symbol parameter conditions min typ max unit t res(tim) timer resolution --1- t timxclk f timxclk = 48 mhz - 20.8 - ns f ext timer external clock frequency on ch1 to ch4 -- f timxclk /2 -mhz f timxclk = 48 mhz - 24 - mhz t max_count 16-bit timer maximum period -- 2 16 - t timxclk f timxclk = 48 mhz - 1365 - s 32-bit timer maximum period -- 2 32 - t timxclk f timxclk = 48 mhz - 89.48 - s
electrical characteristics stm32f030x4/x6/x8/xc 72/93 ds9773 rev 4 6.3.19 communication interfaces i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. wh en configured as open-drain, the pmos connected between the i/o pin and v ddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/os characteristics. all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 55. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 kh z clock but the microcontroller inte rnal rc frequency can vary from 30 to 60 khz. moreover, given an ex act rc oscillator frequency, the ex act timings still depend on the phasing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.1 409.6 ms /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 table 56. wwdg min/max timeout value at 48 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0853 5.4613 ms 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906
ds9773 rev 4 73/93 stm32f030x4/x6/x8/xc electrical characteristics 75 spi characteristics unless otherwise specified, the parameters given in table 58 for spi are derived from tests performed under the ambient temperature, f pclkx frequency and supply voltage conditions summarized in table 21: general operating conditions . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics. table 57. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns table 58. spi characteristics (1) symbol parameter con ditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 15 pf - 6 ns t su(nss) nss setup time slave mode 4tpclk - ns t h(nss) nss hold time slave mode 2tpclk + 10 - t w(sckh) t w(sckl) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 -2 tpclk/2 + 1 t su(mi) t su(si) data input setup time master mode 4 - slave mode 5 - t h(mi) data input hold time master mode 4 - t h(si) slave mode 5 - t a(so) (2) data output access time slave mode, f pclk = 20 mhz 0 3tpclk t dis(so) (3) data output disable time slave mode 0 18 t v(so) data output valid time slave mode (after enable edge) - 22.5 t v(mo) data output valid time master mode (after enable edge) - 6 t h(so) data output hold time slave mode (after enable edge) 11.5 - t h(mo) master mode (after enable edge) 2 - ducy(sck) spi slave input clock duty cycle slave mode 25 75 % 1. data based on characterization re sults, not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and th e max time is for the maximum time to put the data in hi-z
electrical characteristics stm32f030x4/x6/x8/xc 74/93 ds9773 rev 4 figure 25. spi timing diagram - slave mode and cpha = 0 figure 26. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . ai14135b nss input t su(nss) t c(sck) t h(nss) sck input cpha=1 cpol=0 cpha=1 cpol=1 t w(sckh) t w(sckl) t a(so) t v(so) t h(so) t r(sck) t f(sck) t dis(so) miso output mosi input t su(si) t h(si) msb out msb in bit6 out lsb out lsb in bit 1 in
ds9773 rev 4 75/93 stm32f030x4/x6/x8/xc electrical characteristics 75 figure 27. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . ai14136c sck output cpha= 0 mosi output miso inp ut cpha= 0 lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck output cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) msb in bit6 in msb out
package information stm32f030x4/x6/x8/xc 76/93 ds9773 rev 4 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 lqfp64 package information lqfp64 is 64-pin, 10 x 10 mm low-profile quad flat package. figure 28. lqfp64 outline 1. drawing is not to scale. table 59. lqfp64 mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 5w_me_v3 a1 a2 a seating plane ccc c b c c a1 l l1 k identification pin 1 d d1 d3 e 1 16 17 32 33 48 49 64 e3 e1 e gauge plane 0.25 mm
ds9773 rev 4 77/93 stm32f030x4/x6/x8/xc package information 89 figure 29. lqfp64 recommended footprint 1. dimensions are expr essed in millimeters. b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - d3 - 7.500 - - 0.2953 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 59. lqfp64 mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 48 32 49 64 17 1 16 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909c
package information stm32f030x4/x6/x8/xc 78/93 ds9773 rev 4 device marking the following figure gives an example of topside marking orientation versus pin 1 identifier location. the printed markings may differ depending on the supply chain. other optional marking or inse t/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 30. lqfp64 marking example (package top view) 1. parts marked as es or e or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contac ted prior to any decision to use these engineering samples to run a qualification activity. msv36475v1 product identification (1) pin 1 identifier revision code date code stm32f030 rct6 y ww r
ds9773 rev 4 79/93 stm32f030x4/x6/x8/xc package information 89 7.2 lqfp48 package information lqfp48 is a 48-pin, 7 x 7 mm low-profile quad flat package figure 31. lqfp48 outline 1. drawing is not to scale. table 60. lqfp48 mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 5b_me_v2 pin 1 identification ccc c c d3 0.25 mm gauge plane b a1 a a2 c a1 l1 l d d1 e3 e1 e e 12 1 13 24 25 36 37 48 seating plane k
package information stm32f030x4/x6/x8/xc 80/93 ds9773 rev 4 figure 32. lqfp48 recommended footprint 1. dimensions are expr essed in millimeters. e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 60. lqfp48 mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911d 13 48
ds9773 rev 4 81/93 stm32f030x4/x6/x8/xc package information 89 device marking the following figure gives an example of topside marking orientation versus pin 1 identifier location. the printed markings may differ depending on the supply chain. other optional marking or inse t/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 33. lqfp48 marking example (package top view) 1. parts marked as es or e or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contac ted prior to any decision to use these engineering samples to run a qualification activity. stm32f msv36476v1 030cct6 r yww product identification (1) revision code date code pin 1 identifier
package information stm32f030x4/x6/x8/xc 82/93 ds9773 rev 4 7.3 lqfp32 package information lqfp32 is a 32-pin, 7 x 7 mm low-profile quad flat package figure 34. lqfp32 outline 1. drawing is not to scale. table 61. lqfp32 mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 d d1 d3 e3 e1 e 1 8 9 16 17 24 25 32 a1 l1 l k a1 a2 a c b gauge plane 0.25 mm seating plane c pin 1 identification ccc c 5v_me_v2 e
ds9773 rev 4 83/93 stm32f030x4/x6/x8/xc package information 89 figure 35. lqfp32 recommended footprint 1. dimensions are expr essed in millimeters. b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.100 - - 0.0039 1. values in inches are converted from mm and rounded to 4 decimal digits. table 61. lqfp32 mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 5v_fp_v2 1 8 9 16 17 24 25 32 9.70 7.30 7.30 1.20 0.30 0.50 1.20 6.10 9.70 0.80 6.10
package information stm32f030x4/x6/x8/xc 84/93 ds9773 rev 4 device marking the following figure gives an example of topside marking orientation versus pin 1 identifier location. the printed markings may differ depending on the supply chain. other optional marking or inse t/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 36. lqfp32 marking example (package top view) 1. parts marked as es or e or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contac ted prior to any decision to use these engineering samples to run a qualification activity. stm32f msv36477v1 030k6t6 r yww product identification (1) revision code date code pin 1 identification
ds9773 rev 4 85/93 stm32f030x4/x6/x8/xc package information 89 7.4 tssop20 pac kage information tssop20 is a 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch package. figure 37. tsso p20 outline 1. drawing is not to scale. table 62. tssop20 mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 d 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 4.300 4.400 4.500 0.1693 0.1732 0.1772 e - 0.650 - - 0.0256 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ya_me_v3 1 20 c c l e e1 d a2 a k e b 10 11 a1 l1 aaa seating plane c gauge plane 0.25 mm pin 1 identification
package information stm32f030x4/x6/x8/xc 86/93 ds9773 rev 4 figure 38. tssop20 footprint 1. dimensions are expr essed in millimeters. k 0 - 8 0 - 8 aaa - - 0.100 - - 0.0039 1. values in inches are converted fr om mm and rounded to four decimal digits. table 62. tssop20 mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. ya_fp_v1 7.10 4.40 0.25 0.25 6.25 1.35 0.40 0.65 1.35 1 20 11 10
ds9773 rev 4 87/93 stm32f030x4/x6/x8/xc package information 89 device marking the following figure gives an example of topside marking orientation versus pin 1 identifier location. the printed markings may differ depending on the supply chain. other optional marking or inse t/upset marks, which identify the parts throughout supply chain operations, are not indicated below. figure 39. tssop20 marking example (package top view) 1. parts marked as es or e or accompanied by an engi neering sample notification letter are not yet qualified and therefore not approved for use in production. st is not responsible for any consequences resulting from such use. in no event will st be liable for t he customer using any of these engineering samples in production. st's quality department must be contac ted prior to any decision to use these engineering samples to run a qualification activity. msv36478v1 revision code date code device identification (1) pin 1 identification 32f030f4p6 ywwr
package information stm32f030x4/x6/x8/xc 88/93 ds9773 rev 4 7.5 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 21: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-am bient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd - v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.5.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org table 63. package thermal characteristics symbol parameter value unit j thermal resistance junction-ambient lqfp64 - 10 mm x 10 mm 44 c/w thermal resistance junction-ambient lqfp48 - 7 mm x 7 mm 55 thermal resistance junction-ambient lqfp32 - 7 mm x 7 mm 56 thermal resistance junction-ambient tssop20 - 6.5 mm x 6.4 mm 76
ds9773 rev 4 89/93 stm32f030x4/x6/x8/xc ordering information 89 8 ordering information + for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest st sales office. example : stm32 f 030 c 6 t 6 x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 030 = stm32f030xx pin count f = 20 pins k = 32 pins c = 48 pins r = 64 pins code size 4 = 16 kbyte of flash memory 6 = 32 kbyte of flash memory 8 = 64 kbyte of flash memory c = 256 kbyte of flash memory package p = tssop t = lqfp temperature range 6 = ?40 to 85 c option xxx = programmed parts tr = tape and reel
revision history stm32f030x4/x6/x8/xc 90/93 ds9773 rev 4 9 revision history table 64. document revision history date revision changes 04-jul-2013 1 initial release. 15-jan-2015 2 extended the applicabilit y to stm32f030xc. updated: ? features and table device summary, ? section: description, ? table: stm32f030x4/6/8/c family device features and peripheral counts, ? figure: block diagram, ? section: memories, ? section: general-purpose inputs/outputs (gpios), ? section: universal synchronous/asynchronous receiver transmitters (usart), ? table: stm32f030x4/6/8/c pin definitions, ? table: alternate functions selected through gpioa_afr registers for port a, ? table: alternate functions selected through gpiob_afr registers for port b ? table: alternate functions selected through gpioc_afr registers for port c ? table: alternate functions selected through gpiod_afr registers for port d, ? table: alternate functions selected through gpiof_afr registers for port f, ? section: emc characteristics, ? section: part numbering. added device marking examples: ? figure: lqfp64 marking example (package top view), ? figure: lqfp48 marking example (package top view), ? figure: lqfp32 marking example (package top view), ? figure: tssop20 marking example (package top view). 23-jan-2017 3 updated: ? table 2: stm32f030x4/x6/x8/xc family device features and peripheral counts ? figure 1: block diagram and figure footnotes ? figure 2: clock tree of stm32f030x4/x6/x8 and figure footnotes ? section 3.11: timers and watchdogs - number of timers, counts of complementary outputs in the table and the footnotes
ds9773 rev 4 91/93 stm32f030x4/x6/x8/ xc revision history 92 23-jan-2017 3 ? section 3.11.2: general-purpose timers (tim3, tim14..17) - number of timers ? table 5: timer feature comparison - footnotes added ? table 7: stm32f030x4/x6/x8/xc i 2 c implementation - fm+ and footnote ? figure 4 through figure 7 - darker highlight on pins ? table 11: stm32f030x4/6/8/c pin definitions - corrections ? table 12: alternate functions selected through gpioa_afr registers for port a - note order ? table 14 through table 16 - corrected footnotes ? figure 10: stm32f030x4/x6/x8/xc memory map footnote ? figure 13: power supply scheme ? table 24: embedded internal reference voltage : added t start , changed v refint and t s_vrefint values and notes ? table 25: typical and maximum current consumption from v dd supply at v dd = 3.6 v footnotes ? table 26: typical and maximum current consumption from the v dda supply values for stm32f030xc and footnotes ? table 34: lse oscillator characteristics (f lse = 32.768 khz) lsedrv[1:0] values removed (see ref. manual) ? table 50: adc characteristics - t stab defined relative to clock frequency; notes 3. and 4. added ? section 3.14: universal synchronous/asynchronous receiver/transmitter (usart) - introduction and table 8: stm32f0x0 usart implementation ? figure 10: stm32f030x4/x6/x8/xc memory map footnote ? table 43: esd absolute maximum ratings - c4 or c3 class, depending on device variant; cdm values updated to match the referenced standard. (cdm standard was updated in the previous release, without duly modifying the related values.) ? table 53: ts characteristics : removed the min. value for t start and parameter name change ? figure 19 and figure 20 improved ? section 7: package information name and structure change ? section 8: ordering information renamed from part numbering table 64. document revision history (continued) date revision changes
revision history stm32f030x4/x6/x8/xc 92/93 ds9773 rev 4 15-jan-2019 4 ? figure 2 split in two figures ? tim15 complementary outputs count in table 5 ? periodic wakeup unit feature in section 3.12: real- time clock (rtc) ? driver enable for usart 6 in ta ble 8 ? number of supported auto baud rate detection modes corrected in table 8 ? af4 and af5 for pb10 in table 13 ? notes in table 14 , table 15 , and table 16 ? extension of table 16 ?v fesd class in table 41 table 64. document revision history (continued) date revision changes
ds9773 rev 4 93/93 stm32f030x4/x6/x8/xc 93 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2019 stmicroelectronics ? all rights reserved

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